1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a magnetic tunnel junction (MTJ) device and its fabricating method.
2. Description of the Related Art
MRAM (Magnetic Random Access memory) is a non-volatile magnetic random access memory, which has the advantages of high speed access to static random access memory (SRAM), high integration of dynamic random access memory (DRAM), and almost infinite writing cycles. As such, MRAMs have attracted attention.
A conventional MRAM performs its storage function based on its magnetic tunnel junction (MTJ) structure and electron spin polarization effect. Research on MRAMs, which are also used as sensors, is ongoing.
FIGS. 1 to 5 are cross-sectional views associated with a conventional MTJ. FIG. 1 is a simplified cross-sectional view of a semiconductor device having an underlying layer 103 (herein, only a part of the device is shown for simplicity), a first dielectric layer 100 formed on layer 103, a tungsten plug formed in the first dielectric layer 100 and in contact with layer 103, and a second dielectric layer 102 formed on the first dielectric layer 100. As shown in FIG. 2, an opening is formed in second dielectric layer 102, and MTJ 104 is formed in the opening. As shown in FIG. 2, MTJ 104 includes, in part, a top electrode 1041, a first synthetic anti-ferromagnetic material (SAF) layer 1042, a tunnel dielectric layer 1043, a second synthetic anti-ferromagnetic material (SAF) layer 1044, an anti-ferromagnetic pinning layer 1045 and a bottom electrode 1046. The first SAF layer 1042 further includes, in part, a first free sublayer (ferromagnetic material), a Ru layer and a second free sublayer (ferromagnetic material). Since the first SAF layer 1042 includes such a tri-layered structure, magnetic flux will loop within it, thus reducing flux leakage. The second SAF 1044 layer has a similar tri-layered structure as well. Although the second SAF 1044 layer is pinned by the anti-ferromagnetic pinning layer 1045 beneath, in some implementations it is not necessary to pin the second SAF 1044, and thus the anti-ferromagnetic pinning layer 1045 can be omitted. Further, although magnetic flux loopings toward the same direction are shown (see solid arrows) in the figure, the loop direction of magnetic flux lines in the first SAF 1042 can be reversed to represent the storage of 1 or 0.
FIG. 2 shows an MTJ structure. Following the processes used to from the MTJ as shown in FIG. 2, the MTJ 104 is patterned with a mask. For example, the MTJ 104 is etched, merely a portion of the MTJ 104 located on the contact 101 is retained as shown in FIG. 3. In conventional MTJ processes, etching method such as FIB or plasma etching or the like can be used for the purpose of lowering cost and achieving minimized MTJ pattern. Next, as shown in FIG. 4, a dielectric layer 105 is deposited and planarized to fill up the opening. Last, within the opening an electric contact, for example, a tungsten plug is formed for the MTJ 104 and a metal layer 106 is disposed on the second dielectric layer 102.
In the existing techniques, in order to enhance the magnetism of ferromagnetic materials (Fe, Co, Ni), it is common to add Fe component to various ferromagnetic materials. Generally, a ferromagnetic material contains about 80% Co, about 19% Ni, and about 1% Fe, and it is important to add Fe to ferromagnetic materials for their magnetism. Different manufactures provide different ferromagnetic material compositions. Nevertheless, Fe component is always added for magnetism enhancement.
However, adding Fe is incompatible with CMOS processes, while Ni and Co are common elements used in CMOS processes. Since Fe is incompatible with CMOS processes, the manufacture of MTJ can not share a manufacturing line of CMOS processes, and additional equipments need to be provided. For example, when depositing a multi-layer MTJ structure, some dedicated equipments should be additionally introduced to construct a Fe-contained MTJ multi-layer structure. In subsequent processes, moreover, other dedicated etching equipments are needed to etch the Fe-contained MTJ multi-layer structure as well.
Further, for magnetism enhancement, a tri-layered synthetic anti-ferromagnetic material layer is employed to enable magnetic flux to loop between a first sublayer and a second sublayer to prevent the magnetic flux leakage. However, the tri-layered structure may lead to an increased size of devices, which is disadvantageous for semiconductor devices with increasingly reduced dimensions.
On the other hand, as is well known, the tunnel dielectric layer 1043 has a thickness of about only 1-2 nanometers. When the layer 1043 is etched as shown in FIG. 3, it is exposed by the etching step, and the edge of the tunnel dielectric layer 1043 is damaged in the etching process, which is disadvantageous to a MTJ for memory devices. Damaged tunnel dielectric layer 1043 may increase leakage current and error rate of stored data. Therefore, in the prior art, MTJ based etching processes have very low yield rate, resulting in the need to introduce dedicated equipments that are often expensive.
In summary, all of above may increase MTJ manufacturing cost.
On the other hand, in practice, there are many sophisticated manufacturing lines for CMOS. Hence, it would be ideal to fabricate MTJ with CMOS processes.